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Scan IF Registers
24-42 Scan IF
SIFCTL2, Scan IF Control Register 2
15 14 13 12 11 10 9 8
SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
SIFSH SIFTEN SIFTCH1x SIFTCH0x
SIFTCH1
OUT
SIFTCH0
OUT
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
SIFDACON
Bit 15 DAC on. Setting this bit turns the DAC on regardless of the TSM control.
0 The DAC is controlled by the TSM.
1 The DAC is on.
SIFCAON
Bit 14 Comparator on. Setting this bit turns the comparator on regardless of the TSM
control.
0 The comparator is controlled by the TSM.
1 The comparator is on.
SIFCAINV
Bit 13 Invert comparator output
0 Comparator output is not inverted
1 Comparator output is inverted
SIFCAX
Bit 12 Comparator input select. This bit selects groups of signals for the comparator
input.
0 Comparator input is one of the SIFCHx channels, selected with the
channel select logic.
1 Comparator input is one of the SIFCIx channels, selected with the
channel select logic and the SIFCISEL and SIFCACI3 bits.
SIFCISEL
Bit 11 Comparator input select. This bit is used with the SIFCACI3 bit to select the
comparator input when SIFCAX = 1.
0 Comparator input is one of the SIFCIx channels, selected with the
channel select logic and SIFCACI3 bit.
1 Comparator input is the SIFCI channel
SIFCACI3
Bit 10 Comparator input select. This bit is selects the comparator input when
SIFCISEL = 0 and SIFCAX = 1.
0 Comparator input is selected with the channel select logic.
1 Comparator input is SIFCI3.
SIFVSS
Bit 9 Sample-and-hold SIFV
SS
select.
0 The ground connection of the sample capacitor is connected to SIFV
SS
,
regardless of the TSM control.
1 The ground connection of the sample capacitor is controlled by the TSM