Filter
Top Products
SD16_A Operation
22-10 SD16_A
22.2.8 Conversion Memory Register: SD16MEM0
The SD16MEM0 register is associated with the SD16_A channel. Conversion
results are moved to the SD16MEM0 register with each decimation step of the
digital filter. The SD16IFG bit is set when new data is written to SD16MEM0.
SD16IFG is automatically cleared when SD16MEM0 is read by the CPU or
may be cleared with software.
Output Data Format
The output data format is configurable in two’s complement, offset binary or
unipolar mode as shown in Table 22−2.The data format is selected by the
SD16DF and SD16UNI bits.
Table 22−2.Data Format
SD16UNI SD16DF Format Analog Input SD16MEM0
†
Digital Filter Output
(OSR =256)
+FSR FFFF FFFFFF
00
Bipolar
Offset
ZERO 8000 800000
00
Offset
Binary
−FSR 0000 000000
+FSR
7FFF 7FFFFF
01
Bipolar
Two’s
ZERO 0000 000000
01
Two’s
compliment
−FSR 8000 800000
+FSR
FFFF FFFFFF
1 X Unipolar
ZERO 0000 800000
1 X Unipolar
−FSR 0000 000000
†
Independent of SD16OSRx and SD16XOSR settings; SD16LSBACC = 0.
Figure 22−5 shows the relationship between the full-scale input voltage range
from −V
FSR
to +V
FSR
and the conversion result. The data formats are
illustrated.
Figure 22−5. Input Voltage vs. Digital Output
Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
7FFFh
8000h
Bipolar Output: 2’s complement
Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
FFFFh
8000h
Bipolar Output: Offset Binary
0000h
0000h
Input
Voltage
SD16MEMx
−V
FSR
+V
FSR
FFFFh
Unipolar Output
0000h