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8.2.7 Using DMA with System Interrupts
DMA transfers are not interruptible by system interrupts. System interrupts
remain pending until the completion of the transfer. NMI interrupts can
interrupt the DMA controller if the ENNMI bit is set.
System interrupt service routines are interrupted by DMA transfers. If an
interrupt service routine or other routine must execute with no interruptions,
the DMA controller should be disabled prior to executing the routine.
8.2.8 DMA Controller Interrupts
Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any
mode, when the corresponding DMAxSZ register counts to zero. If the
corresponding DMAIE and GIE bits are set, an interrupt request is generated.
All DMAIFG flags source only one DMA controller interrupt vector and the
interrupt vector is shared with the DAC12 module. Software must check the
DMAIFG and DAC12IFG flags to determine the source of the interrupt. The
DMAIFG flags are not reset automatically and must be reset by software.