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Scan IF Operation
24-23Scan IF
PSM Counters
The PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updated
with Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be read
via the SIFCNT register. If the SIFCNTRST bit is set, each read access will
reset the counters, otherwise the counters remain unchanged when read. If
a count event occurs during a read access the count is postponed until the end
of the read access but multiple count events during a read access will
increment the counters only once. When SIFEN = 0, both counters are held
in reset.
SIFCNT1 can increment or decrement based on Q1 and Q2. When
SIFCNT1ENM = 1, SIFCNT1 decrements on a transition to a state where bit
Q2 is set. When SIFCNT1ENP = 1, SIFCNT1 increments on a transition to a
state where bit Q1 is set. When both bits SIFCNT1ENM and SIFCNT1ENM are
set, and both bits Q1 and Q2 are set on a state transition, SIFCNT1 does not
increment or decrement.
SIFCNT2 decrements based on Q2. When SIFCNT2EN = 1, SIFCNT2
decrements on a transition to a state where bit Q2 is set. On the first count after
a reset SIFCNT2 will roll over from zero to 255 (0FFh).
When the next state is calculated to be the same state as the current state, the
counters SIFCNT1 and SIFCNT2 are incremented or decremented according
to Q1 and Q2 at the state transition. For example, if the current state is 05h and
Q2 is set, and if the next state is calculated to be 05h, the transition from state
05h to 05h will decrement SIFCNT2 if SIFCNT2EN = 1.