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8-21
DMAxCTL, DMA Channel x Control Register
15 14 13 12 11 10 9 8
Reserved
DMADTx DMADSTINCRx DMASRCINCRx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
DMA
DSTBYTE
DMA
SRCBYTE
DMALEVEL DMAEN DMAIFG DMAIE
DMA
ABORT
DMAREQ
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
Reserved
Bit 15 Reserved
DMADTx
Bits
14−12
DMA Transfer mode.
000 Single transfer
001 Block transfer
010 Burst-block transfer
011 Burst-block transfer
100 Repeated single transfer
101 Repeated block transfer
110 Repeated burst-block transfer
111 Repeated burst-block transfer
DMA
DSTINCRx
Bits
11−10
DMA destination increment. This bit selects automatic incrementing or
decrementing of the destination address after each byte or word transfer.
When DMADSTBYTE=1, the destination address increments/decrements by
one. When DMADSTBYTE=0, the destination address
increments/decrements by two. The DMAxDA is copied into a temporary
register and the temporary register is incremented or decremented. DMAxDA
is not incremented or decremented.
00 Destination address is unchanged
01 Destination address is unchanged
10 Destination address is decremented
11 Destination address is incremented
DMA
SRCINCRx
Bits
9−8
DMA source increment. This bit selects automatic incrementing or
decrementing of the source address for each byte or word transfer. When
DMASRCBYTE=1, the source address increments/decrements by one.
When DMASRCBYTE=0, the source address increments/decrements by
two. The DMAxSA is copied into a temporary register and the temporary
register is incremented or decremented. DMAxSA is not incremented or
decremented.
00 Source address is unchanged
01 Source address is unchanged
10 Source address is decremented
11 Source address is incremented
DMA
DSTBYTE
Bit 7 DMA destination byte. This bit selects the destination as a byte or word.
0 Word
1 Byte