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8-22
DMA
SRCBYTE
Bit 6 DMA source byte. This bit selects the source as a byte or word.
0 Word
1 Byte
DMA
LEVEL
Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive
triggers.
0 Edge sensitive (rising edge)
1 Level sensitive (high level)
DMAEN
Bit 4 DMA enable
0 Disabled
1 Enabled
DMAIFG
Bit 3 DMA interrupt flag
0 No interrupt pending
1 Interrupt pending
DMAIE
Bit 2 DMA interrupt enable
0 Disabled
1 Enabled
DMA
ABORT
Bit 1 DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI.
0 DMA transfer not interrupted
1 DMA transfer was interrupted by NMI
DMAREQ
Bit 0 DMA request. Software-controlled DMA start. DMAREQ is reset
automatically.
0 No DMA start
1 Start DMA
DMAxSA, DMA Source Address Register
15 14 13 12 11 10 9 8
DMAxSAx
rw rw rw rw rw rw rw rw
76543210
DMAxSAx
rw rw rw rw rw rw rw rw
DMAxSAx Bits
15−0
DMA source address. The source address register points to the DMA source
address for single transfers or the first source address for block transfers. The
source address register remains unchanged during block and burst-block
transfers.