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Scan IF Operation
24-5Scan IF
Figure 24−2. Scan IF Analog Front End Block Diagram
SIFTESTD
SIFTESTS1(tsm)
+
−
1
0
SIFCH0
SIFCH1
SIFCH2
00
01
10
11
SIFCH3
1
0
SIFCI
SIFCISEL
SIFCAON
SIFCAX
SIFCACI3
10
11
01
00
SIFTCH0x
2
SIFTCH1x
SIF2OUT
SIF3OUT
SIFTCH0OUT
SIF1OUT
SIF0OUT
SIFTCH1OUT
SIFCAINV
SIFRSON(tsm)
2
Output Stage
SIFCHx(tsm)
2
Sync.
00
01
10
11
00
01
10
11
S/H
S/H
S/H
SIFVSS
SIFCOM
Sample/Hold
2
DAC 10 Bit
SIFDACR0
SIFDACR1
SIFDACR2
SIFDACR3
SIFDACR4
SIFDACR5
SIFDACR6
SIFDACR7
SIFSH
SIFCA(tsm)
SIFDAC(tsm)
SIFDACON
SIFCI0
SIFCI1
SIFCI2
SIFCI3
S/H
VMID
SIFVCC2
00
01
10
11
Excit
Excit
Excit
Excit
SIFTEN
Excitation
SIFLCEN(tsm)
SIFEX(tsm)
TESTDX