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LCD_A Controller Operation
19-5LCD_A Controller
19.2.3 LCD_A Voltage And Bias Generation
The LCD_A module allows selectable sources for the peak output waveform
voltage, V1
,
as well as the fractional LCD biasing voltages V2 − V5. V
LCD
may
be sourced from AV
CC
, an internal charge pump, or externally.
All internal voltage generation is disabled if the oscillator sourcing ACLK is
turned off (OSCOFF = 1) or the LCD_A module is disabled (LCDON = 0).
LCD Voltage Selection
V
LCD
is sourced from AV
CC
when VLCDEXT = 0, VLCDx = 0, and VREFx =
0. V
LCD
is sourced from the internal charge pump when VLCDEXT = 0,
VLCDPEN = 1, and VLCDx > 0. The charge pump is always sourced from
DV
CC.
The VLCDx bits provide a software selectable LCD voltage from 2.6 V
to 3.44 V (typical) independent of DV
CC
. See the device-specific datasheet for
specifications.
When the internal charge pump is used, a 4.7 µF or larger capacitor must be
connected between pin LCDCAP and ground. Otherwise, irreversible damage
can occur. When the charge pump is enabled, peak currents of 2 mA typical
occur on DV
CC.
However, the charge pump duty cycle is approximately
1/1000, resulting in a 2 µA average current. The charge pump may be
temporarily disabled by setting LCDCPEN = 0 with VLCDx > 0 to reduce
system noise. In this case, the voltage present at the external capacitor is used
for the LCD voltages until the charge pump is re-enabled.
Note: Capacitor Required For Internal Charge Pump
A 4.7 µF or larger capacitor must be connected from pin LCDCAP to ground
when the internal charge pump is enabled. Otherwise, damage can occur.
The internal charge pump may use an external reference voltage when
VLCDREFx = 01. In this case, the charge pump voltage will be 3x the voltage
applied externally to the LCDREF pin and the VLCDx bits are ignored.
When VLCDEXT = 1, V
LCD
is sourced externally from the LCDCAP pin and
the internal charge pump is disabled. The charge pump and internal bias
generation require an input clock source of 32768 Hz +/− 10%. If neither is
used, the input clock frequency may be different per the application needs.
LCD Bias Generation
The fractional LCD biasing voltages, V2 − V5 can be generated internally or
externally, independent of the source for V
LCD
. The LCD bias generation block
diagram is shown in Figure 19−3.