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Table 8−2.DMA Trigger Operation
DMAxTSELx Operation
0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset
when the transfer starts
0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is
automatically reset when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2
CCIFG flag will not trigger a transfer.
0010 A transfer is triggered when the TBCCR2 CCIFG flag is set. The TBCCR2 CCIFG flag is
automatically reset when the transfer starts. If the TBCCR2 CCIE bit is set, the TBCCR2
CCIFG flag will not trigger a transfer.
0011 A transfer is triggered when USART0 receives new data. In I
2
C mode, the trigger is the
data-received condition, not the RXRDYIFG flag. RXRDYIFG is not cleared when the transfer
starts, and setting RXRDYIFG with software will not trigger a transfer. If RXRDYIE is set, the
data received condition will not trigger a transfer. In UART or SPI mode, a transfer is triggered
when the URXIFG0 flag is set. URXIFG0 is automatically reset when the transfer starts. If
URXIE0 is set, the URXIFG0 flag will not trigger a transfer.
0100 A transfer is triggered when USART0 is ready to transmit new data. In I
2
C mode, the trigger
is the transmit-ready condition, not the TXRDYIFG flag. TXRDYIFG is not cleared when the
transfer starts, and setting TXRDYIFG with software will not trigger a transfer. If TXRDYIE is
set, the transmit ready condition will not trigger a transfer. In UART or SPI mode, a transfer is
triggered when the UTXIFG0 flag is set. UTXIFG0 is automatically reset when the transfer
starts. If UTXIE0 is set, the UTXIFG0 flag will not trigger a transfer.
0101 A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL
DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_0CTL
DAC12IE bit is set, the DAC12_0CTL DAC12IFG flag will not trigger a transfer.
0110 A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are
performed, the corresponding ADC12IFGx is the trigger. When sequences are used, the
ADC12IFGx for the last conversion in the sequence is the trigger. A transfer is triggered when
the conversion is completed and the ADC12IFGx is set. Setting the ADC12IFGx with software
will not trigger a transfer. All ADC12IFGx flags are automatically reset when the associated
ADC12MEMx register is accessed by the DMA controller.
0111 A transfer is triggered when the TACCR0 CCIFG flag is set. The TACCR0 CCIFG flag is
automatically reset when the transfer starts. If the TACCR0 CCIE bit is set, the TACCR0
CCIFG flag will not trigger a transfer.
1000 A transfer is triggered when the TBCCR0 CCIFG flag is set. The TBCCR0 CCIFG flag is
automatically reset when the transfer starts. If the TBCCR0 CCIE bit is set, the TBCCR0
CCIFG flag will not trigger a transfer.
1001 A transfer is triggered when the URXIFG1 flag is set. URXIFG1 is automatically reset when
the transfer starts. If URXIE1 is set, the
URXIFG1 flag will not trigger a transfer.
1010 A transfer is triggered when the UTXIFG1 flag is set. UTXIFG1 is automatically reset when
the transfer starts. If UTXIE1 is set, the UTXIFG1 flag will not trigger a transfer
.
1011 A transfer is triggered when the hardware multiplier is ready for a new operand.
1100 No transfer is triggered.
1101 No transfer is triggered.
1110 A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG
triggers channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are
automatically reset when the transfer starts.
1111 A transfer is triggered by the external trigger DMAE0.