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FLL+ Clock Module Operation
4-7FLL+ Clock Module
4.2.4 Digitally-Controlled Oscillator (DCO)
The DCO is an integrated ring oscillator with RC-type characteristics. The
DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by
N, the lowest 7 bits of the SCFQCTL register.
The DCOPLUS bit sets the f
DCOCLK
frequency to f
DCO
or f
DCO/D
. The FLLDx
bits configure the divider, D, to 1, 2, 4 or 8. By default, DCOPLUS = 0 and D
= 2 providing a clock frequency of f
DCO/2
on f
DCOCLK
.
The multiplier (N+1) and D set the frequency of DCOCLK.
DCOPLUS = 0: f
DCOCLK
= (N + 1) x f
ACLK
DCOPLUS = 1: f
DCOCLK
= D x (N + 1) x f
ACLK
DCO Frequency Range
The frequency range of f
DCO
is selected with the FNx bits as listed in
Table 4−1. The range control allows the DCO to operate near the center of the
available taps for a given DCOCLK frequency. The user must ensure that
MCLK does not exceed the maximum operating frequency. See the
device-specific datasheet for parameters.
Table 4−1.DCO Range Control Bits
FN_8 FN_4 FN_3 FN_2 Typical f
DCO
Range
0 0 0 0 0.65−6.1
0 0 0 1 1.3−12.1
001 X 2−17.9
0 1 X X 2.8−26.6
1
X X X 4.2−46
4.2.5 Frequency Locked Loop (FLL)
The FLL continuously counts up or down a 10-bit frequency integrator. The
output of the frequency integrator that drives the DCO can be read in SCFI1
and SCFI0. The count is adjusted +1 or −1 with each ACLK crystal period.
Five of the integrator bits, SCFI1 bits 7-3, set the DCO frequency tap.
Twenty-nine taps are implemented for the DCO (28, 29, 30, and 31 are
equivalent), and each is approximately 10% higher than the previous. The
modulator mixes two adjacent DCO frequencies to produce fractional taps.
SCFI1 bits 2-0 and SCFI0 bits 1-0 are used for the modulator.
The DCO starts at the lowest tap after a PUC or when SCFI0 and SCFI1 are
cleared. Time must be allowed for the DCO to settle on the proper tap for
normal operation. 32 ACLK cycles are required between taps requiring a worst
case of 28 x 32 ACLK cycles for the DCO to settle.