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Instruction Set
3-25
RISC 16−Bit CPU
BIC[.W] Clear bits in destination
BIC.B Clear bits in destination
Syntax BIC src,dst or BIC.W src,dst
BIC.B src,dst
Operation .NOT.src .AND. dst −> dst
Description The inverted source operand and the destination operand are logically
ANDed. The result is placed into the destination. The source operand is not
affected.
Status Bits Status bits are not affected.
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The six MSBs of the RAM word LEO are cleared.
BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO)
Example The five MSBs of the RAM byte LEO are cleared.
BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO