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ADC12 Operation
20-18 ADC12
20.2.10 ADC12 Interrupts
The ADC12 has 18 interrupt sources:
- ADC12IFG0-ADC12IFG15
- ADC12OV, ADC12MEMx overflow
- ADC12TOV, ADC12 conversion time overflow
The ADC12IFGx bits are set when their corresponding ADC12MEMx memory
register is loaded with a conversion result. An interrupt request is generated
if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV
condition occurs when a conversion result is written to any ADC12MEMx
before its previous conversion result was read. The ADC12TOV condition is
generated when another sample-and-conversion is requested before the
current conversion is completed.
ADC12IV, Interrupt Vector Generator
All ADC12 interrupt sources are prioritized and combined to source a single
interrupt vector. The interrupt vector register ADC12IV is used to determine
which enabled ADC12 interrupt source requested an interrupt.
The highest priority enabled ADC12 interrupt generates a number in the
ADC12IV register (see register description). This number can be evaluated or
added to the program counter to automatically enter the appropriate software
routine. Disabled ADC12 interrupts do not affect the ADC12IV value.
Any access, read or write, of the ADC12IV register automatically resets the
ADC12OV condition or the ADC12TOV condition if either was the highest
pending interrupt. Neither interrupt condition has an accessible interrupt flag.
The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits
are reset automatically by accessing their associated ADC12MEMx register
or may be reset with software.
If another interrupt is pending after servicing of an interrupt, another interrupt
is generated. For example, if the ADC12OV and ADC12IFG3 interrupts are
pending when the interrupt service routine accesses the ADC12IV register, the
ADC12OV interrupt condition is reset automatically. After the RETI instruction
of the interrupt service routine is executed, the ADC12IFG3 generates another
interrupt.