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SD16_A Operation
22-8 SD16_A
Digital Filter Output
The number of bits output by the digital filter is dependent on the oversampling
ratio and ranges from 15 to 30 bits. Figure 22−4 shows the digital filter output
and their relation to SD16MEM0 for each OSR, LSBACC, and SD16UNI
setting. For example, for OSR = 1024, LSBACC = 1, and SD16UNI = 1, the
SD16MEM0 register contains bits 28 − 13 of the digital filter output. When OSR
= 32, the one (SD16UNI = 0) or two (SD16UNI=1) LSBs are always zero.
The SD16LSBACC and SD16LSBTOG bits give access to the least significant
bits of the digital filter output. When SD16LSBACC = 1 the 16 least significant
bits of the digital filter’s output are read from SD16MEM0 using word
instructions. The SD16MEM0 register can also be accessed with byte
instructions returning only the 8 least significant bits of the digital filter output.
When SD16LSBTOG = 1 the SD16LSBACC bit is automatically toggled each
time SD16MEM0 is read. This allows the complete digital filter output result to
be read with two reads of SD16MEM0. Setting or clearing SD16LSBTOG does
not change SD16LSBACC until the next SD16MEM0 access.
Figure 22−4. Used Bits of Digital Filter Output
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=0, SD16UNI=0
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=1, SD16UNI=0
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=0, SD16UNI=1
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=1, SD16UNI=1
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=0, SD16UNI=0
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=1, SD16UNI=0
04812162024 153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=0, SD16UNI=1
048121620
24
153269723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=1, SD16UNI=1