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LCD_A Controller Operation
19-8 LCD_A Controller
19.2.4 LCD Timing Generation
The LCD_A controller uses the f
LCD
signal from the integrated ACLK prescaler
to generate the timing for common and segment lines. ACLK is assumed to
be 32768 Hz for generating f
LCD
. The f
LCD
frequency is selected with the
LCDFREQx bits. The proper f
LCD
frequency depends on the LCD’s
requirement for framing frequency and the LCD multiplex rate and is
calculated by:
f
LCD
= 2 × mux × f
Frame
For example, to calculate f
LCD
for a 3-mux LCD, with a frame frequency of
30 - 100Hz:
f
Frame
(from LCD datasheet) = 30 - 100 Hz
f
LCD
= 2 × 3 × f
Frame
f
LCD(min)
= 180 Hz
f
LCD(max)
= 600 Hz
select f
LCD
= 32768/128 = 256 Hz or 2768/96 = 341 Hz or 32768/64 = 512 Hz.
The lowest frequency has the lowest current consumption. The highest
frequency has the least flicker.
19.2.5 LCD Outputs
Some LCD segment, common, and Rxx functions are multiplexed with digital
I/O functions. These pins can function either as digital I/O or as LCD functions.
The pin functions for COMx and Rxx, when multiplexed with digital I/O, are
selected using the applicable PxSELx bits as described in the Digital I/O
chapter. The LCD segment functions, when multiplexed with digital I/O, are
selected using the LCDSx bits in the LCDAPCTLx registers.
The LCDSx bits selects the LCD function in groups of four pins. When LCDSx
= 0, no multiplexed pin is set to LCD function. When LCDSx = 1, the complete
group of four is selected as LCD function.
Note: LCDSx Bits Do Not Affect Dedicated LCD Segment Pins
The LCDSx bits only affect pins with multiplexed LCD segment functions and
digital I/O functions. Dedicated LCD segment pins are not affected by the
LCDSx bits.