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SD16 Registers
21-21SD16
SD16IFG
Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results are
available. SD16IFG is automatically reset when the corresponding
SD16MEMx register is read, or may be cleared with software.
0 No interrupt pending
1 Interrupt pending
SD16SC
Bit 1 SD16 start conversion
0 No conversion start
1 Start conversion
SD16GRP
Bit 0 SD16 group. Groups SD16 channel with next higher channel. Not used for
the last channel.
0 Not grouped
1 Grouped
SD16INCTLx, SD16 Channel x Input Control Register
76543210
SD16INTDLYx SD16GAINx SD16INCHx
rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0
SD16
INTDLYx
Bits
7-6
Interrupt delay generation after conversion start. These bits select the
delay for the first interrupt after conversion start.
00 Fourth sample causes interrupt
01 Third sample causes interrupt
10 Second sample causes interrupt
11 First sample causes interrupt
SD16GAINx
Bits
5-3
SD16 preamplifier gain
000 x1
001 x2
010 x4
011 x8
100 x16
101 x32
110 Reserved
111 Reserved
SD16INCHx
Bits
2-0
SD16 channel differential pair input
000 Ax.0
001 Ax.1
010 Ax.2
011 Ax.3
100 Ax.4
101 Ax.5
110 Ax.6- Temperature Sensor
111 Ax.7- Short for PGA offset measurement