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Theory of Operation
3–48
1780R-Series Service Manual
high to remove the readout engine’s address from the bus. The Control PAL then
waits until the Master MPU raises /HOLDA, signifying its return to bus control.
At this point the PAL enters the normal idle state to wait for the first Master
MPU cycle.
DRAM Memory. The DRAM consists of four identical 64K × 4 addressable
memory chips. Each chip outputs 4 bits of the 16-bit memory word to the data
bus AD. Each chip has row and column enable inputs along with a write enable.
As configured, U150 and U155 are the lower bank of the memory and are
controlled by either the /RAS (which also controls the higher bank) or the
/LCAS which is lower bank specific. U150 and U155 output data bits AD0
through AD7. U157 and U160 are the higher bank of memory and it also is
controlled by the /RAS, but relies on the /HCAS to switch to column addresses
and output data bits AD8 through AD15.
The circuit board contains mountings for 1M × 4 memory chips (U151, U156,
U158, and U161) to support potential custom modifications, should more
memory be required.