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Theory of Operation
3–74
1780R-Series Service Manual
al transconductance amplifiers used in sample-and-hold circuits. The demodu-
lated chrominance that is fed back drives the negative input; the positive input is
driven by a Position control DC reference voltage (from the Master MPU).
At the middle of horizontal sync a PAL (located on Diagram 27) generates the
Center Dot Clamp pulse, which is the bias input to the operational amplifiers
(U138 and U337). The bias inputs turn on the amplifiers to transfer the voltage
level from the negative input to the hold capacitors (C136 and C341). The charge
stored in the hold capacitors, output through source followers Q135 and Q342, is
the bias input to the Demodulators (U128 and U541).
Demodulators. U128 and U541 are double balanced demodulators, whose outputs
are voltages proportional to the phase difference between the signal input (pins 1
and 4) and the carrier input (pins 8 and 10). The signal inputs are driven by
chrominance from the Gain Cell (Diagram 27). The carrier inputs are driven by
continuous sine-wave signals from the Subcarrier Regenerator (Diagram 31). The
carrier input for the R-Y Demodulator (U128) is the IF
SC
output; the B-Y
Demodulator (U541) carrier input is the QF
SC
, which is quadrature delayed in
the Subcarrier Regenerator. Fine adjustment of Quad Phase (C850) changes the
phase relationship between the + and – carrier inputs to the B-Y Demodulator.
Demodulator gains are set by adjusting a variable resistance (R227 for the
vertical and R542 for the horizontal) between emitters of the signal input
differential amplifier.
Low-Pass Filters. The Demodulator outputs are filtered by identical four-pole
low-pass filters with Q122 and Q223 as the active elements for the vertical filter
and Q739 and Q841 as the active elements in the horizontal filter. The low-pass
filters remove the high-frequency components of the demodulation process, and
determine the bandwidth of the vector mode signal path to control the rise time
and delay of the demodulated signal.