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Theory of Operation
1780R-Series Service Manual
3–101
information. This delay information is loaded into the three counters, U333,
U336, and U339. At any given time, only one cursor delay can be active; Cursor
1 and Cursor 2 time share at a 30 Hz rate. Cursor 1 and Cursor 2 delays are
selected by a clock steering decoder, U329, which latches data in from the
Microprocessor Data Bus. U239 and U233 latch the data for Timing Cursor 2,
while U236 and U243 latch the data for Timing Cursor 1. The correct latch pair
is selected by the outputs from U223A, a D-type flip-flop, that is clocked from
the Freq Cal Timer.
The discrete counters are wired in series to form a single 12-bit counter. Each
counter element is driven by 4 bits that preset its delay. The counter clock is a
10-MHz TTL pulse from the synchronized LC Oscillator comparator output. The
ripple carry out of U339 drives U218B, to generate the Ramp Start pulse. The
Ramp Start pulse from U218B also clears U223B. The Q output of U223B loads
the latch count into the counters. U223B is preset by a /COUNTER ENABLE
pulse that starts the LC Oscillator and restarts the cycle.