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Theory of Operation
3–94
1780R-Series Service Manual
U400B is clocked by U261 when either /RD or /WR goes low while /Fltr Brd is
low. An Exclusive OR gate internal to U261 outputs the INC pulse and
increments the Address Counter. Incrementing the Address Counter toggles the
A0 (U271-14) output, which is the other input to the U261 Exclusive OR gate,
that resets the INC pulse after one address count. The /BYPASS clears U400B
and U271 to reset the initial starting conditions.
CPU Bus Interface. When /Fltr Brd and /MA inputs to U410A are low, A8
determines whether the 8-bit MPU Address Bus has access to the lower 8 bits
(U241 [M0 – M7]) of Storage data (A8 low) or the upper 4 bits (U260 [M8 –
M11]) of data (A8 high). /RD, from the CPU Access, determines the direction of
data exchange.
Memory Write Control. The Memory Write Control uses the R/W pulse to control
storage of data for full field, VITS, and freeze line modes in 525/60 or 625/50
systems. In full field operation, a state machine, built from a Programmable
Logic Array (U280) and a 12-bit Binary Counter (U281), is used as a half-line
counter to assert the WE output during the vertical interval and halt generation of
the R/W pulse, which prevents writing to Storage. The counter is synchronized
to a vertical rate pulse, V Sel. The /PAL input sets the video standard (high for
525/60 or low for 625/50).
When /LSE counter input is low, WE is generated only when U280 accepts a line
select pulse, W Linesel F. If the line select pulse is not present, the Memory data
is echoed to give a bright display of the selected line.
A low on the counter /FL input sets a low on WE to disable writing to Storage
and the data in Storage is output as a frozen signal.
Power Supply. U200 is a post regulator for the –5 volt supply. L421 and C411
decouple the digital +5 volt supply from the +5 volt supply. L210 and C100
provide decoupling for the analog –5 volts. L420 and C420 are the decoupling
for the analog+5 volts.