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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
Programming Model
Page 109 of 377
Implementation Note: The PowerPC Architecture indicates that in some implementations the Move-to
Condition Register Fields (mtcrf) instruction might perform more slowly when only a portion of the fields are
updated as opposed to all of the fields. The Condition Register access latency for the 750GX is the same in
both cases.
Move-to/Move-from Special-Purpose Register Instructions (UISA)
Table 2-32 lists the mtspr and mfspr instructions.
Table 2-33 lists the SPR numbers for both user-level and supervisor-level accesses.
Table 2-32. Move-to/Move-from Special-Purpose Register Instructions (UISA)
Name Mnemonic Syntax
Move-to Special-Purpose Register mtspr SPR,rS
Move-from Special-Purpose Register mfspr rD,SPR
Table 2-33. PowerPC Encodings (Page 1 of 3)
Register Name
SPR
1
Access mfspr/mtspr
Decimal SPR[5–9] SPR[0–4]
CTR 9 00000 01001 User (UISA) Both
DABR 1013 11111 10101 Supervisor (OEA) Both
DAR 19 00000 10011 Supervisor (OEA) Both
DBAT0L 537 10000 11001 Supervisor (OEA) Both
DBAT0U 536 10000 11000 Supervisor (OEA) Both
DBAT1L 539 10000 11011 Supervisor (OEA) Both
DBAT1U 538 10000 11010 Supervisor (OEA) Both
DBAT2L 541 11110 11101 Supervisor (OEA) Both
DBAT2U 540 11110 11100 Supervisor (OEA) Both
DBAT3L 543 11110 11111 Supervisor (OEA) Both
DBAT3U 542 11110 11110 Supervisor (OEA) Both
DBAT4L 569 10001 11001 Supervisor (OEA) Both
DBAT4U 568 10001 11000 Supervisor (OEA) Both
DBAT5L 571 10001 11011 Supervisor (OEA) Both
DBAT5U 570 10001 11010 Supervisor (OEA) Both
DBAT6L 573 10001 11101 Supervisor (OEA) Both
DBAT6U 572 10001 11100 Supervisor (OEA) Both
Note:
1. The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding. For mtspr and mfspr
instructions, the SPR number coded in assembly language does not appear directly as a 10-bit binary number in the instruction.
The number coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five bits appearing in bits
16–20 of the instruction and the low-order five bits in bits 11–15.
2. The TB Registers are referred to as TBRs rather than SPRs and can be written to using the mtspr instruction in supervisor mode
and the TBR numbers here. The TB Registers can be read in user mode using either the mftb or mfspr instruction and specifying
TBR 268 for TBL and SPR 269 for TBU.