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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction-Cache and Data-Cache Operation
Page 136 of 377
gx_03.fm.(1.2)
March 27, 2006
3.4.2.6 Instruction Cache Block Invalidate (icbi)
For the icbi instruction, the effective address is not computed or translated, so it cannot generate a protection
violation or exception. This instruction performs a virtual lookup into the instruction cache (index only). All
ways of the selected instruction cache set are invalidated.
The icbi instruction is not broadcast on the 60x bus. The icbi instruction invalidates the cache blocks inde-
pendent of whether the cache is disabled or locked.
3.5 Cache Operations
This section describes the 750GX’s cache operations.
3.5.1 Cache-Block-Replacement/Castout Operations
Both the instruction and data cache use a pseudo least-recently-used (PLRU) replacement algorithm when a
new block needs to be placed in the cache. When the data to be replaced is in the modified (M) state, that
data is written into a castout buffer while the missed data is being accessed on the bus. When the load
completes, the 750GX then pushes the replaced cache block from the castout buffer to the L2 cache (if L2 is
enabled) or to main memory (if L2 is disabled).
The replacement logic first checks to see if there are any invalid blocks in the set and chooses the lowest-
order, invalid block (L[0–7]) as the replacement target. If all eight blocks in the set are valid, the PLRU algo-
rithm is used to determine which block should be replaced. The PLRU algorithm is shown in Figure 3-5 on
page 137.
Each cache is organized as eight blocks per set by 128 sets. There is a valid bit for each block in the cache,
L[0–7]. When all eight blocks in the set are valid, the PLRU algorithm is used to select the replacement target.
There are seven PLRU bits, B[0–6] for each set in the cache. For every hit in the cache, the PLRU bits are
updated using the rules specified in Table 3-2 on page 138.