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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006
Instruction Timing
Page 237 of 377
6.6.1 Branch, Dispatch, and Completion-Unit Resource Requirements
This section describes the specific resources required to avoid stalls during branch resolution, instruction
dispatching, and instruction completion.
6.6.1.1 Branch-Resolution Resource Requirements
The following branch instructions and resources are required to avoid stalling the fetch unit in the course of
branch resolution:
• The bclr instruction requires LR availability.
• The bcctr instruction requires CTR availability.
• Branch and link instructions require shadow LR availability.
• The “branch conditional on counter decrement and the CR” condition requires CTR availability or the CR
condition must be false, and the 750GX cannot execute instructions after an unresolved predicted branch
when the BPU encounters a branch.
• A branch conditional on CR condition cannot be executed following an unresolved predicted branch
instruction.
6.6.1.2 Dispatch-Unit Resource Requirements
The following resources are required to avoid stalls in the dispatch unit. IQ0 and IQ1 are the two dispatch
entries in the instruction queue:
• Requirements for dispatching from IQ0 are:
– Needed execution unit available.
– Needed GPR Rename Registers available.
– Needed FPR Rename Registers available.
– Completion queue is not full.
– A completion-serialized instruction is not being executed.
• Requirements for dispatching from IQ1 are:
– Instruction in IQ0 must dispatch.
– Instruction dispatched by IQ0 is not completion- or refetch-serialized.
– Needed execution unit is available after dispatch from IQ0.
– Needed GPR Rename Registers are available after dispatch from IQ0.
– Needed FPR Rename Register is available after dispatch from IQ0.
– Completion queue is not full after dispatch from IQ0.
6.6.1.3 Completion-Unit Resource Requirements
The following is a list of resources required to avoid stalls in the completion unit. Note that the two completion
entries are described as CQ0 and CQ1, where CQ0 is the completion queue located at the end of the
completion queue (see Figure 6-4 on page 218).
• Requirements for completing an instruction from CQ0:
– Instruction in CQ0 must be finished.
– Instruction in CQ0 must not follow an unresolved predicted branch.
– Instruction in CQ0 must not cause an exception.