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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction Timing
Page 218 of 377
gx_06.fm.(1.2)
March 27, 2006
Figure 6-4. Instruction Flow Diagram
SRUIU2
FPU
Complete (Retire)
Fetch
LSU
Dispatch
Branch
Instruction Queue
Completion Queue
Completion Queue
IU1
Store Queue
Processing Unit
(In program order)
Assignment
(In program order)
CQ5 CQ4 CQ3 CQ2 CQ1 CQ0
IQ5 IQ4 IQ3 IQ2 IQ1 IQ0
(Maximum of two instructions per clock cycle;
(Maximum of four instructions per clock cycle)
Reservation
Stations
one instruction per unit)