Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 286 of 377
gx_08.fm.(1.2)
March 27, 2006
8.2.2 Miss-under-Miss
To improve processor performance, a feature called miss-under-miss (MuM) has been added which makes
better use of the address pipelining function of the 60x bus and memory subsystem. It does this by looking
deeper into the L/S unit and starting the process of fetching pending load misses in a pipelined fashion on the
bus. Past versions of the 750 family supported limited pipelining where cache-inhibited stores and castouts
could be pipelined with instruction and data reloads. Reloads, however, consumed a majority of the bus
cycles and were not pipelined into other reloads, stalling the processor for instructions or data. Enabling MuM
now allows four reloads or cache-inhibited loads to be pipelined in a continuous fashion on the 60x bus, with
the BIU keeping track of requests, addreesses, and pipelining.
Note: The MuM only works because the the 60x bus is an in-order transfer. If it was a transaction type bus
(out of order with tags), then the L/S and Dcache would need the extra queues as well.
The data cache allows hits under one miss, but stalls for a second miss until the first miss is reloaded. The
MuM feature enables a second request queue to the L2 cache for handling up to four misses. If there is a hit
in the L2 cache for a data-cache miss-under-miss, then the L2 data is held until needed for allocation in the
DBWO
(data-bus write-
only)
Assertion indicates that the 750GX might perform the data-bus tenure for an
outstanding write address even if a read address is pipelined before the write
address. If DBWO
is asserted, the 750GX will assume data-bus mastership for a
pending data-bus write operation. The 750GX will take the data bus for a pending
read operation if this input is asserted along with DBG
and no write is pending.
Care must be taken with DBWO
to ensure the desired write is queued (for
example, a cache-line snoop push-out operation).
DBB
(data bus busy) Assertion by the 750GX indicates that the 750GX is the data-bus master. The
750GX always assumes data-bus mastership if it needs the data bus and is given a
qualified data-bus grant (see DBG
).
For more detailed information on the arbitration signals, see Section 7.2.1,
Address-Bus Arbitration Signals, on page 251, and Section 7.2.6, Data-Bus Arbi-
tration Signals, on page 264.
Figure 8-4. Cache Diagram for Miss-under-Miss Feature
Instruction Cache
Data Cache
L2
Cache
MuM
dld0
dld1
ild
BIU
60x Bus
Load/
dld2
dld3
4 data tenures
Store
Unit
snoop
ild = instruction load
dld = data load