Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006
Instruction Timing
Page 245 of 377
Load Floating-Point
Single Indexed
lfsx 31 535 LSU 2:1 —
Load Halfword
Algebraic
lha 42 — LSU 2:1 —
Load Halfword
Algebraic with Update
lhau 43 — LSU 2:1 —
Load Halfword
Algebraic with Update
Indexed
lhaux 31 375 LSU 2:1 —
Load Halfword
Algebraic Indexed
lhax 31 343 LSU 2:1 —
Load Halfword Byte-
Reverse Indexed
lhbrx 31 790 LSU 2:1 —
Load Halfword and Zero lhz 40 — LSU 2:1 —
Load Halfword and Zero
with Update
lhzu 41 — LSU 2:1 —
Load Halfword and Zero
with Update Indexed
lhzux 31 311 LSU 2:1 —
Load Halfword and Zero
Indexed
lhzx 31 279 LSU 2:1 —
Load Multiple Word lmw 46 — LSU 2 + n
3
Completion, execution
Load String Word
Immediate
lswi 31 597 LSU 2 + n
3
Completion, execution
Load String Word
Indexed
lswx 31 533 LSU 2 + n
3
Completion, execution
Load Word And
Reserve Indexed
lwarx 31 20 LSU 3:1 Execution
Load Word Byte-
Reverse Indexed
lwbrx 31 534 LSU 2:1 —
Load Word and Zero lwz 32 — LSU 2:1 —
Load Word and Zero
with Update
lwzu 33 — LSU 2:1 —
Load Word and Zero
with Update Indexed
lwzux 31 55 LSU 2:1 —
Load Word and Zero
Indexed
lwzx 31 23 LSU 2:1 —
Store Byte stb 38 — LSU 2:1 —
Store Byte with Update stbu 39 — LSU 2:1 —
Store Byte with Update
Indexed
stbux 31 247 LSU 2:1 —
Store Byte Indexed stbx 31 215 LSU 2:1 —
Table 6-9. Load-and-Store Instructions (Page 2 of 4)
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization
1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for
back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete
the instruction to the cache, which stays busy keeping subsequent cache operations from executing.
2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,
throughput is at least 11 cycles.
3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n
is the number of words accessed by the instruction.