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IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_05.fm.(1.2)
March 27, 2006
Memory Management
Page 203 of 377
Figure 5-8. Page-Address-Translation Flow—TLB Hit
(See The
Programming
Environments
Manual)
(See Figure 5-9 on page 205)
(See The Programming
Environments Manual)
TLB Hit
Case
Alignment Exception
Effective Address
Generated
Continue Access to Memory
Subsystem with WIMG-Bits from
PTE
Page Table
Search Operation
PA[0–31]←RPN||A[20–31]
Page Address
Translation
Check Page Memory
Protection Violation Conditions
Instruction Fetch with N-Bit
Set in Segment Descriptor
(No-Execute)
Page Memory
Protection Violation
Access Permitted
Otherwise
Store Access with
PTE [C] = 0
Otherwise
dcbz Instruction
with W or I = 1
Otherwise
(See Figure 5-6 on page 191)
Generate 52-Bit Virtual
Address
Compare Virtual Address
with TLB Entries
Access
Prohibited