Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006
Bus Interface Operation
Page 289 of 377
Load multiple and load string instructions allow one MuM (two outstanding miss requests) to pipeline on
the 60x bus.
6. A load is aliased to a store in the store queue, which means it references a byte to the same index and
word. Loads are normally allowed to bypass stores in the 3-deep store queue. However, a load that
aliases a store must allow the store to proceed ahead of it (in program order). The aliased store can start
an MuM, but load MuM will wait until the alias condition is complete.
7. There is a cache inhibit (CI), eieio, or sync instruction in the store queue.
Loads can bypass stores in the store queue, providing the store queue does not contain a CI, eieio, or
sync instruction. MuM is prohibited while these instructions are executing.
8. Store queue in LSU is full (three entries).
Once the store queue is full, and another store is dispatched, then the stores must be allowed to empty.
In this state, MuM will drop down to two outstanding misses.
9. Exception, DSI, or alignment error.
Any load or store instruction resulting in an exception, DSI, or alignment error will not be serviced for an
MuM.
10. The lwarx, Data Cache Block Touch (dcbt), Data Cache Block Touch for Store (dcbtst), dcbst, dcbf,
dcbz, dcbi, TLB Invalidate Entry (tlbie), and eieio instructions stall MuM requests.
These instructions represent special cache and synchronizing mechanisms that will prevent MuM
requests from starting until they have completed.
11. Cacheable loads will not MuM into cache-inhibited loads, and vice versa.
Mixing cacheable loads with CI loads in the instruction stream prevents MuM requests from executing.
Cacheable loads pipeline into other cacheable loads, but not into cache-inhibited loads. The two types of
loads allow MuM requests only to their respective type.
12. Store misses pipeline to a maximum depth of two outstanding misses as shown below.
Load word A miss
Store word B MuM
.... no further load or store MuM
Store word A miss
Store word B MuM
.... no further load or store MuM
13. Load miss pipeline in BIU to a maximum depth of four outstanding misses (same as the reload-request
queue).
If there are two outstanding requests, two more MuM requests can be issued if the above conditions are
not true and the following conditions are true:
a. The transaction is a load.
b. The load transaction preceding a new MuM request is aligned on a cache-line boundary.
c. There are no outstanding dependencies. For MuM, all operands for the address calculation must be
valid.
d. No preceding MuM request is an L2 cache hit. Once it is determined that an MuM request is an
L2 hit, then no more MuM requests will proceed.
e. The limit for reloads (four) has not been reached.
14. In little-endian mode, MuM is constrained to a maximum depth of two outstanding misses.