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User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
gx_04.fm.(1.2)
March 27, 2006
Exceptions
Page 173 of 377
4.5.14 Instruction Address Breakpoint Exception (0x01300)
An instruction address breakpoint interrupt occurs when the following conditions are met:
• The instruction breakpoint address IABR[0:29] matches EA[0:29] of the next instruction to complete in
program order. The instruction that triggers the instruction address breakpoint exception is not executed
before the exception handler is invoked.
• The translation enable bit (IABR[TE]) matches MSR[IR].
• The breakpoint enable bit (IABR[BE]) is set. The address match is also reported to the JTAG/common on-
chip processor (COP) block, which can subsequently generate a soft or hard reset. The instruction
tagged with the match does not complete before the breakpoint exception is taken.
See Section 2.1.2.1, Instruction Address Breakpoint Register (IABR), on page 64 for the format of the IABR.
Table 4-11 lists register settings when an instruction address breakpoint exception is taken.
The 750GX requires that an mtspr to the IABR be followed by a context-synchronizing instruction. The
750GX cannot generate a breakpoint response for that context-synchronizing instruction if the breakpoint is
enabled by the mtspr instruction to the IABR immediately preceding it. The 750GX also cannot block a
breakpoint response on the context-synchronizing instruction if the breakpoint was disabled by the mtspr
instruction to the IABR immediately preceding it.
When an instruction address breakpoint exception is taken, instruction fetching resumes at offset 0x01300
from the base address indicated by MSR[IP].
4.5.15 System Management Interrupt (0x01400)
The 750GX implements a system management interrupt exception, which is not defined by the PowerPC
Architecture. The system management exception is very similar to the external interrupt exception and is
particularly useful in implementing the nap mode. It has priority over an external interrupt (see Table 4-3 on
page 155), and it uses a different vector in the exception table (offset 0x01400).
Table 4-12 lists register settings when a system management interrupt exception is taken.
Table 4-11. Instruction Address Breakpoint Exception—Register Settings
Register Setting Description
SRR0
Set to the effective address of the instruction that the processor would have attempted to execute next if no excep-
tion conditions were present.
SRR1
0 Loaded with equivalent MSR bits.
1:4 Cleared.
5:9 Loaded with equivalent MSR bits.
10:15 Cleared.
16:31 Loaded with equivalent MSR bits.
MSR
POW 0
ILE —
EE 0
PR 0
FP 0
ME —
FE0 0
SE 0
BE 0
FE1 0
IP —
IR 0
DR 0
PM 0
RI 0
LE Set to value of ILE