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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Programming Model
Page 116 of 377
gx_02.fm.(1.2)
March 27, 2006
Table 2-38 summarizes the cache instructions defined by the VEA. Note that these instructions are acces-
sible to user-level programs.
Table 2-38. User-Level Cache Instructions (Page 1 of 2)
Name Mnemonic Syntax Implementation Notes
Data Cache Block
Touch
1
dcbt rA,rB
The VEA defines this instruction to allow for potential system performance
enhancements through the use of software-initiated prefetch hints. Implementa-
tions are not required to take any action based on execution of this instruction,
but they may prefetch the cache block corresponding to the EA into their cache.
When dcbt executes, the 750GX checks for protection violations (as for a load
instruction). This instruction is treated as a no-op for the following cases:
• A valid translation is not found either in BAT or TLB.
• The access causes a protection violation.
• The page is mapped cache-inhibited, G = 1 (guarded), or T = 1.
• The cache is locked or disabled.
• HID0[NOOPTI] = 1.
Otherwise, if no data is in the cache location, the 750GX requests a cache-line
fill (with intent to modify). Data brought into the cache is validated as if it were a
load instruction. The memory reference of a dcbt sets the reference bit.
Data Cache Block
Touch for Store
1
dcbtst rA,rB This instruction behaves like dcbt.
Data Cache Block Set
to Zero
dcbz rA,rB
The EA is computed, translated, and checked for protection violations. For
cache hits, four beats of zeros are written to the cache block, and the tag is
marked M. For cache misses with the replacement block marked exclusive
unmodified (E), the zero line fill is performed, and the cache block is marked M.
However, if the replacement block is marked M, the contents are written back to
memory first. The instruction executes regardless of whether the cache is
locked. If the cache is disabled, an alignment exception occurs. If M = 1 (coher-
ency enforced), the address is broadcast to the bus before the zero line fill.
The exception priorities (from highest to lowest) are as follows:
1 Cache disabled—Alignment exception
2 Page marked write-through or cache Inhibited—Alignment exception
3 BAT protection violation—DSI exception
4 TLB protection violation—DSI exception
dcbz is the only cache instruction that broadcasts even if HID0[ABE] = 0. This
is done to maintain coherency with other cache devices in the system.
1. A program that uses dcbt and dcbtst instructions improperly performs less efficiently. To improve performance, HID0[NOOPTI]
can be set, which causes dcbt and dcbtst to be no-oped at the cache. These instructions do not cause bus activity and cause only
a 1-clock execution latency. The default state of this bit is zero, which enables the use of these instructions.