Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction Timing
Page 242 of 377
gx_06.fm.(1.2)
March 27, 2006
Table 6-8 shows latencies for floating-point instructions. Pipelined floating-point instructions are shown with
the number of clocks in each pipeline stage separated by dashes. Floating-point instructions with a single
entry in the cycles column are not pipelined. When the FPU executes these nonpipelined instructions, it
remains busy for the full duration of the instruction execution and is not available for subsequent instructions.
Subtract From Carrying subfc[o][.]31 8 IU1/IU2 1—
Subtract From
Extended
subfe[o][.] 31 136 IU1/IU2 1 Execution
Subtract From
Immediate Carrying
subfic 8—IU1/IU21—
Subtract From Minus
One Extended
subfme[o][.] 31 232 IU1/IU2 1 Execution
Subtract From Zero
Extended
subfze[o][.] 31 200 IU1/IU2 1 Execution
Subtract From subf[.]31 40IU1/IU21—
Trap Word tw 31 4 IU1/IU2 2 —
Trap Word Immediate twi 3—IU1/IU22—
XOR Immediate xori 26 — IU1/IU2 1 —
XOR Immediate Shifted xoris 27 — IU1/IU2 1 —
XOR xor[.] 31 316 IU1/IU2 1 —
Table 6-8. Floating-Point Instructions (Page 1 of 2)
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization
Floating Absolute Value fabs[.] 63 264 FPU 1-1-1 —
Floating Add Single fadds[.] 59 21 FPU 1-1-1 —
Floating Add fadd[.] 63 21 FPU 1-1-1 —
Floating Compare
Ordered
fcmpo 63 32 FPU 1-1-1 —
Floating Compare
Unordered
fcmpu 63 0 FPU 1-1-1 —
Floating Convert To
Integer Word with
Round toward Zero
fctiwz[.] 63 15 FPU 1-1-1 —
Floating Convert To
Integer Word
fctiw[.] 63 14 FPU 1-1-1 —
Floating Divide Single fdivs[.]59 18 FPU 17—
Floating Divide fdiv[.]63 18 FPU 31—
Floating Multiply-Add
Single
fmadds[.] 59 29 FPU 1-1-1 —
Floating Multiply-Add fmadd[.] 63 29 FPU 2-1-1 —
Floating Move Register fmr[.] 63 72 FPU 1-1-1 —
Table 6-7. Integer Instructions (Page 3 of 3)
Instruction Mnemonic
Primary
Opcode
Extended
Opcode
Unit Cycles Serialization