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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 190 of 377
gx_05.fm.(1.2)
March 27, 2006
5.1.6.2 Page-Address-Translation Selection
If address translation is enabled and the effective address information does not match a BAT array entry,
then the segment descriptor must be located. When the segment descriptor is located, the T bit in the
segment descriptor selects whether the translation is to a page or to a direct-store segment as shown in
Figure 5-6, General Flow of Page and Direct-Store Interface Address Translation, on page 191.
For 32-bit implementations, the segment descriptor for an access is contained in one of the 16 on-chip
Segment Registers. Effective address bits EA[0–3] select one of the 16 Segment Registers.
Note: The 750GX does not implement the direct-store interface, and accesses to these segments cause a
DSI or ISI exception. In addition, Figure 5-6 shows how the no-execute protection is enforced. If the no-exe-
cute (N) bit in the segment descriptor is set and the access is an instruction fetch, the access is faulted as
described in Chapter 7, “Memory Management,” in the PowerPC Microprocessor Family: The Programming
Environments Manual. Figure 5-6 shows the flow for these cases as described by the PowerPC OEA, and so
the TLB references are shown as optional. Because the 750GX implements TLBs, these branches are valid
and are described in more detail throughout this section.