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User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
Exceptions
Page 170 of 377
gx_04.fm.(1.2)
March 27, 2006
stops dispatching and waits for all pending instructions to complete. This allows any instructions in progress
that need to take an exception to do so before the external interrupt is taken. After all instructions have
vacated the completion buffer, the 750GX takes the external interrupt exception as defined in the PowerPC
Architecture (OEA).
An external interrupt might be delayed by other higher-priority exceptions or if MSR[EE] is cleared when the
exception occurs. Register settings for this exception are described in Chapter 6, “Exceptions” in the
PowerPC Microprocessor Family: The Programming Environments Manual.
When an external interrupt exception is taken, instruction fetching resumes at offset 0x00500 from the phys-
ical base address indicated by MSR[IP].
4.5.6 Alignment Exception (0x00600)
The 750GX implements the alignment exception as defined by the PowerPC Architecture (OEA). An align-
ment exception is initiated when any of the following occurs:
• The operand of a floating-point load or store is not word-aligned.
• The operand of lmw, stmw, lwarx, or stwcx. is not word-aligned.
• The operand of dcbz is in a page which is write-through or caching-inhibited.
• An attempt is made to execute dcbz when the data cache is disabled.
•An eciwx or ecowx is not word-aligned.
• A multiple or string access is attempted with MSR[LE] set.
Note: In the 750GX, a floating-point load or store to a direct-store segment causes a DSI exception rather
than an alignment exception, as specified by the PowerPC Architecture. For more information, see
Section 4.5.3, DSI Exception (0x00300), on page 169.
4.5.7 Program Exception (0x00700)
The 750GX implements the program exception as it is defined by the PowerPC Architecture (OEA). A
program exception occurs when no higher-priority exception exists and one or more of the exception condi-
tions defined in the OEA occur.
The 750GX invokes the system illegal instruction program exception when it detects any instruction from the
illegal instruction class. The 750GX fully decodes the Special Purpose Register (SPR) field of the instruction.
If an undefined SPR is specified, a program exception is taken.
The UISA defines mtspr and mfspr with the record bit (Rc) set as causing a program exception or giving a
boundedly-undefined result (see Section 2.3.1.1, Definition of Boundedly Undefined, on page 87 for more
information). In the 750GX, the appropriate Condition Register (CR) should be treated as undefined. Like-
wise, the PowerPC Architecture states that the Floating Compared Unordered (fcmpu) or Floating Compared
Ordered (fcmpo) instruction with the record bit set can either cause a program exception or provide a
boundedly-undefined result. In the 750GX, the condition register field destination (the BF field) in an instruc-
tion encoding for these cases is considered undefined.
The 750GX does not support either of the two floating-point imprecise modes defined by the PowerPC Archi-
tecture. Unless exceptions are disabled (MSR[FE0] = MSR[FE1] = 0), all floating-point exceptions are treated
as precise.
When a program exception is taken, instruction fetching resumes at offset 0x00700 from the physical base
address indicated by MSR[IP]. Chapter 6, “Exceptions” in the PowerPC Microprocessor Family: The
Programming Environments Manual describes register settings for this exception.