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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
Programming Model
Page 83 of 377
2.2.3 Floating-Point Operand and Execution Models—UISA
The IEEE 754-1985 standard defines conventions for 64-bit and 32-bit arithmetic. The standard requires that
single-precision arithmetic be provided for single-precision operands. The standard permits double-precision
arithmetic instructions to have either (or both) single-precision or double-precision operands, but states that
single-precision arithmetic instructions should not accept double-precision operands.
The PowerPC UISA follows these guidelines:
• Double-precision arithmetic instructions can have single-precision operands but always produce double-
precision results.
• Single-precision arithmetic instructions require all operands to be single-precision and always produce
single-precision results.
For arithmetic instructions, conversion from double to single-precision must be done explicitly by software,
while conversion from single to double-precision is done implicitly by the processor. For the 750GX, single-
precision multiply type instructions usually operate faster than their double-precision equivalents. For details
on instruction timings, see Chapter 6, Instruction Timing, on page 209.
All PowerPC implementations provide the equivalent of the execution models described in Chapter 3.3 of the
PowerPC Microprocessor Family: The Programming Environments Manual to ensure that identical results are
obtained. The definition of the arithmetic instructions for infinities, denormalized numbers, and not a numbers
(NaNs) follow the conventions described in that section.
Although the double-precision format specifies an 11-bit exponent, exponent arithmetic uses two additional
bit positions to avoid potential transient overflow conditions. An extra bit is required when denormalized
double-precision numbers are prenormalized. A second bit is required to permit computation of the adjusted
exponent value in the following examples when the corresponding exception enable bit is one:
• Underflow during multiplication using a denormalized operand
• Overflow during division using a denormalized divisor
The 750GX provides hardware support for all single and double-precision floating-point operations for most
value representations and all rounding modes. This architecture provides for hardware to implement a
floating-point system as defined in ANSI/IEEE standard 754-1985, IEEE Standard for Binary Floating Point
Arithmetic. Detailed information about the floating-point execution model can be found in Chapter 3,
“Operand Conventions” in the PowerPC Microprocessor Family: The Programming Environments Manual.
2.2.3.1 Denormalized Number Support
The 750GX supports denormalized numbers in hardware. When loading or storing a single-precision denor-
malized number, the load/store unit converts between the internal double-precision format and the external
single-precision format.
2.2.3.2 Non-IEEE Mode (Nondenormalized Mode)
The 750GX supports a nondenormalized mode of operation. In this mode, when a denormalized result is
produced, a default result of zero is generated. The generated zero will have the same sign as the denormal-
ized number. This mode is not strictly IEEE compliant. The 750GX is in this mode when the Floating-Point
non-IEEE Enable (NI) bit of the Floating-Point Status and Control Register (FPSCR) is set.