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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction-Cache and Data-Cache Operation
Page 142 of 377
gx_03.fm.(1.2)
March 27, 2006
3.6.3 Snooping
The 750GX maintains data-cache coherency in hardware by coordinating activity between the data cache,
the bus interface logic, the L2 cache, and the memory system. The 750GX has a copy-back cache which
relies on bus snooping to maintain cache coherency with other caches in the system. For the 750GX, the
coherency size of the bus is the size of a cache block, 32 bytes. This means that any bus transactions that
cross an aligned 32-byte boundary must present a new address onto the bus at that boundary for proper
snoop operation by the 750GX, or they must operate noncoherently with respect to the 750GX.
As bus operations are performed on the bus by other bus masters, the 750GX’s bus snooping logic monitors
the addresses and transfer attributes that are referenced. The 750GX snoops the bus transactions during the
cycle that TS
is asserted for any of the following qualified snoop conditions:
• The global signal (GBL
) is asserted indicating that coherency enforcement is required.
• A reservation is currently active in the 750GX as the result of an lwarx instruction, and the transfer type
attributes (TT[0–4]) indicate a write or kill operation. These transactions are snooped regardless of
whether GBL
is asserted to support reservations in the MEI cache protocol.
All transactions snooped by the 750GX are checked for correct address-bus parity. Every assertion of TS
detected by the 750GX (whether snooped or not) must be followed by an accompanying assertion of address
acknowledge (AACK
).
Once a qualified snoop condition is detected on the bus, the snooped address associated with TS
is
compared against the data-cache tags, memory queues, and/or other storage elements as appropriate. The
L1 data-cache tags and L2 cache tags are snooped for standard data-cache-coherency support. No snooping
is done in the instruction cache for coherency.
The memory queues are snooped for pipeline collisions and memory coherency collisions. A pipeline collision
is detected when another bus master addresses any portion of a line that this 750GX’s data cache is currently
in the process of loading (L1 loading from L2, or L1/L2 loading from memory). A memory coherency collision
occurs when another bus master addresses any portion of a line that the 750GX has currently queued to write
to memory from the data cache (castout or copy-back), but has not yet been granted bus access to perform.
If a snooped transaction results in a cache hit or pipeline collision or memory queue collision, the 750GX
asserts ARTRY
on the 60x bus. The current bus master, detecting the assertion of the ARTRY signal, should
cancel the transaction and retry it at a later time, so that the 750GX can first perform a write operation back to
memory from its cache or memory queues. The 750GX might also retry a bus transaction if it is unable to
snoop the transaction on that cycle due to internal resource conflicts. Additional snoop action might be
forwarded to the cache as a result of a snoop hit in some cases (a cache push of modified data, or a cache-
block invalidation). There is no immediate way for another CPU bus agent to determine the cause of the
750GX ARTRY
.
Implementation Note: Snooping of the memory queues for pipeline collisions, as described above, is
performed for burst read operations in progress only. In this case, the read address has completed on the
bus; however, the data tenure might be either in-progress or not yet started by the processor. During this time
the 750GX will retry any other global access to that line by another bus master until all data has been
received in its L1 cache. Pipeline collisions, however, do not apply for burst write operations in progress. If the
750GX has completed an address tenure for a burst write, and is currently waiting for a data-bus grant or is
currently transferring data to memory, it will not generate an address retry to another bus master that
addresses the line. It is the responsibility of the memory system to handle this collision (usually by keeping