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IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 204 of 377
gx_05.fm.(1.2)
March 27, 2006
5.4.5 Page Table-Search Operation
If the translation is not found in the TLBs (a TLB miss), the 750GX initiates a table-search operation, which is
described in this section. Formats for the PTE are given in “PTE Format for 32-Bit Implementations,” in
Chapter 7, “Memory Management” of the PowerPC Microprocessor Family: The Programming Environments
Manual.
The following is a summary of the page-table-search process performed by the 750GX.
1. The 32-bit physical address of the primary page-table-entry group (PTEG) is generated as described in
“Page Table Addresses” in Chapter 7, “Memory Management” of the PowerPC Microprocessor Family:
The Programming Environments Manual.
2. The first PTE (PTE0) in the primary PTEG is read from memory if cache is enabled. PTE reads occur with
an implied WIM memory/cache mode control bit setting of 0b001. Therefore, they are considered cache-
able, read (burst) from memory, and placed in the cache.
3. The PTE in the selected PTEG is tested for a match with the virtual page number (VPN) of the access.
The VPN is the VSID concatenated with the page index field of the virtual address. For a match to occur,
the following must be true:
– PTE[H] = 0
– PTE[V] = 1
– PTE[VSID] = VA[0–23]
– PTE[API] = VA[24–29]
4. If a match is not found, step 3 is repeated for each of the other seven PTEs in the primary PTEG. If a
match is found, the table-search process continues as described in step 8. If a match is not found within
the eight PTEs of the primary PTEG, the address of the secondary PTEG is generated.
5. The first PTE (PTE0) in the secondary PTEG is read from memory if cache is enabled. Again, because
PTE reads have a WIM bit combination of 0b001, an entire cache line is read into the on-chip cache.
6. The PTE in the selected secondary PTEG is tested for a match with the virtual page number (VPN) of the
access. For a match to occur, the following must be true:
– PTE[H] = 1
– PTE[V] = 1
– PTE[VSID] = VA[0–23]
– PTE[API] = VA[24–29]
7. If a match is not found, step 6 is repeated for each of the other seven PTEs in the secondary PTEG. If it is
never found, an exception is taken (step 9).
8. If a match is found, the PTE is written into the on-chip TLB and the R bit is updated in the PTE in memory
(if necessary). If there is no memory-protection violation, the C bit is also updated in memory (if the
access is a write operation), and the table search is complete.
9. If a match is not found within the eight PTEs of the secondary PTEG, the search fails, and a page-fault
exception condition occurs (either an ISI exception or a DSI exception).
Figure 5-9 on page 205 and Figure 5-10 on page 206 show how the conceptual model for the primary and
secondary page table-search operations, described in the PowerPC Microprocessor Family: The Program-
ming Environments Manual, are realized in the 750GX.
Figure 5-9 shows the case of a dcbz instruction that is executed with W = 1 or I = 1, and that the R bit can be
updated in memory (if required) before the operation is performed or the alignment exception occurs. The R
bit can also be updated if memory protection is violated.