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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_10.fm.(1.2)
March 27, 2006
Power and Thermal Management
Page 347 of 377
10.4.2.4 Power Saving Modes and TAU Operation
The static power saving modes provided by the 750GX (the nap, doze, and sleep modes) allow the tempera-
ture of the processor to be lowered quickly, and can be invoked through the use of the TAU and associated
thermal-management interrupt. The TAU remains operational in the nap and doze modes, and in sleep mode
as long as the SYSCLK signal input remains active. If the SYSCLK signal is made static when sleep mode is
invoked, the TAU is rendered inactive. If the 750GX is entering sleep mode with SYSCLK disabled, the TAU
should be configured to disable thermal-management interrupts, to avoid an unwanted thermal-management
interrupt when the SYSCLK input signal is restored.
TAU Calibration Offset
Due to process and thermal sensor variations, a temperature offset is provided and can be read via an mfspr
instruction to THRM4. The TOFFSET field is an 8-bit signed integer that represents the temperature offset
measured, and it is burned into the THRM4 Register at test to allow for enhanced accuracy. When in TAU
single- or dual-threshold mode, TOFFSET should be subtracted from the desired temperature before setting
the THRMn(THRESHOLD) field. In junction temperature determination mode, TOFFSET must be added to
the final threshold number to determine the temperature.
The temperature, in °C, equals:
THRMn[THRESHOLD] + sign-extended [TOFFSET]
10.5 Instruction-Cache Throttling
The 750GX provides an instruction-cache throttling mechanism to effectively reduce the instruction execution
rate without the complexity and overhead of dynamic clock control. Instruction-cache throttling, when used in
conjunction with the TAU and the dynamic power management capability, provides the system designer with
a flexible means of controlling device temperature while allowing the processor to continue operating.
The instruction-cache throttling mechanism simply throttles the instruction forwarding from the instruction
cache to the instruction buffer. Normally, the instruction cache forwards four instructions to the instruction
buffer every clock cycle if all the instructions hit in the cache. For thermal management, the 750GX provides
a supervisor-level Instruction Cache Throttling Control (ICTC) Special Purpose Register (SPR). The instruc-
tion forwarding rate is reduced by writing a nonzero value into the ICTC[FI] field, and enabling instruction-
cache throttling by setting the ICTC[E] bit to 1. An overall junction temperature reduction can result in proces-
sors that implement dynamic power management by reducing the power to the execution units while waiting
for instructions to be forwarded from the instruction cache. Thus, instruction-cache throttling does not provide
thermal reduction unless HID0[DPM] is set to 1.
A description of the ICTC Register and its bit fields can be found at Section 2.1.3 on page 77.
Note: During instruction-cache throttling, the configuration of the PLL remains unchanged.
Figure 10-5. Instruction Cache Throttling Control SPR Diagram
31
23
Reserved
Forwarding Interval
0
ICTC
E
3022
SPR[5:9][0:4] =[11111][11011]