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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 200 of 377
gx_05.fm.(1.2)
March 27, 2006
Each TLB contains 128 entries organized as a 2-way set-associative array with 64 sets as shown in
Figure 5-7 for the DTLB (the ITLB organization is the same). When an address is being translated, a set of
two TLB entries is indexed in parallel with the access to a Segment Register. If the address in one of the two
TLB entries is valid and matches the 40-bit virtual page number, that TLB entry contains the translation. If no
match is found, a TLB miss occurs.
Unless the access is the result of an out-of-order access, a hardware table-search operation begins if there is
a TLB miss. If the access is out of order, the table-search operation is postponed until the access is required,
at which point the access is no longer out of order. When the matching PTE is found in memory, it is loaded
into the TLB entry selected by the LRU replacement algorithm, and the translation process begins again, this
time with a TLB hit.
Figure 5-7. Segment Register and DTLB Organization
T
078 31
0
15 T VSID
Segment Registers
V
DTLB
0
63
V
EA[0–31]
EA[0–3]
EA[14–19]
VSID
Select
Compare
Compare
EA[4–13]
Line 1
Line 0
MUX
RPN
Line1/Line 0 Hit
PA[0–19]