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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_01.fm.(1.2)
March 27,2006
PowerPC 750GX Overview
Page 33 of 377
The 750GX supports the following types of memory translation:
If translation is enabled, the appropriate MMU translates the higher-order bits of the effective address into
physical address bits by using either BATs or the page translation method. The lower-order address bits,
which are untranslated and therefore, considered both logical and physical, are directed to the L1 caches
where they form the index into the 8-way set-associative tag and data arrays. After translating the address,
the MMU passes the higher-order physical address bits to the cache, and the cache lookup completes. For
caching-inhibited accesses or accesses that miss in the cache, the untranslated lower-order address bits are
concatenated with the translated higher-order address bits. The resulting 32-bit physical address is used and
accesses the L2 cache or system memory via the 60x bus.
If the BAT Registers are enabled and the address translates via this method, the page translation is canceled
and the high-order physical address bits from the BAT Register are forward to the cache/memory access
system. There are eight 8-byte BAT Registers, which function like an associative memory. These registers
provide cache-control and protection information as well as address translation. Only one of the eight BAT
entries should translate a given effective address.
If address relocation is enabled and the effective address does not translate via the BAT method, the virtual-
page method is used. The four high-order bits of the effective address are used to access the 16-entry
Segment Register array. From this array, a 24-bit Segment Register is accessed and used to form the high-
order bits of a 52-bit virtual address. The low-order 28 bits of the effective address are used to form the low-
order bits of the virtual address. This 52-bit virtual address is translated into a physical address by doing a
lookup in the TLB. If the lookup is successful, a physical address is formed by using 16 low-order bits from the
virtual address and 16 high-order bits from the TLB. The TLB also provides cache-control and protection
information to be used by the cache/memory system.
TLBs are 128-entry, 2-way, set-associative caches that contain information about recently translated virtual
addresses. When an address translation is not in a TLB, the 750GX automatically generates a page table
search in memory to update the TLB. This search could find the desired entry in the L1 or L2 cache or in the
page table in memory. The time to reload a TLB entry depends on where it is found; it could be completed in
just a few cycles. If memory is searched, a maximum of 16 bus cycles would be needed before a page-fault
exception is signaled.
1.2.4 On-Chip Level 1 Instruction and Data Caches
The 750GX implements separate instruction and data caches. Each cache is 32-KB and 8-way set-associa-
tive. The caches are physically indexed. Each cache block contains eight contiguous words from memory that
are loaded from an 8-word boundary (bits EA[27–31] are zeros); thus, a cache block never crosses a page
boundary. A miss in the L1 cache causes a block reload from either the L2 cache, if the block is in the L2
cache, or from main memory. The critical double word is accessed first, forwarded to the load/store unit, and
Real-addressing mode In this mode, translation is disabled (control bit MSR(IR) = 0 for instructions and
control bit MSR(DR) = 0 for data). The effective address is used as the physical
address to access memory.
Virtual-page-address
translation
Translates from an effective address to a physical address by using the Segment
Registers and the TLB and access data from a 4-KB virtual page. This page is
either in physical memory or on disk. If the latter, a page-fault exception occurs.
Block-address
translation
Translates the effective address into a physical address by using the BAT Regis-
ters and accesses a block (128 KB to 256 MB) in memory.