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User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
gx_04.fm.(1.2)
March 27, 2006
Exceptions
Page 175 of 377
The thermal-management interrupt is similar to the system management and external interrupt. The 750GX
requires the next instruction in program order to complete or take an exception, blocks completion of any
following instructions, and allows the completed store queue to drain. Any exceptions encountered in this
process are taken first, and the thermal-management interrupt exception is delayed until a recoverable halt is
achieved, at which point the 750GX saves the machine state, as shown in Table 4-13. When a thermal-
management interrupt exception is taken, instruction fetching resumes at offset 0x01700 from the base
address indicated by MSR[IP].
Chapter 10, Power and Thermal Management, on page 335 gives the details about thermal management.
4.5.17 Data Address Breakpoint Exception
The Data Address Breakpoint Register (DABR) is a Special Purpose Register that can cause a data-storage
exception (DSI). When enabled, data addresses are compared with an effective address that is stored in the
DABR (bits 0:28). The granularity of these compares is a double-word. Bit 29 is the translation enable bit and
is compared with the MSR[DR] bit. Bit 30 is a store enable. Bit 31 is a load enable. The DABR is enabled by
setting either the data store enable (DW) or data read enabled (DR) bit. The format of the DABR register is
shown in Section 4.5.17.1 on page 175.
4.5.17.1 Data Address Breakpoint Register (DABR)
For a full description of this register, see the PowerPC Microprocessor Family: The Programming Environ-
ments Manual.
4.5.18 Soft Stops
Both trace and breakpoint exception conditions will generate a soft stop instead of an exception if soft stop
has been enabled by the JTAG/COP logic. If trace and instruction breakpoint conditions occur simulta-
neously, instruction breakpoint takes priority over trace in both the exception and soft stop enabled cases.
A soft stop can also be generated with a request from the COP. This request is treated like an external excep-
tion, except that it is nonmaskable and generates a soft stop instead of an exception.
If soft stop is enabled, only one soft stop will be generated before completion of an instruction with an IABR
match. This holds true if a soft stop is generated before that instruction for any other reason, such as trace
mode on for the preceding instruction or a COP soft stop request.
DAB BT
DW
DR
012345678910111213141516171819202122232425262728293031
Bits Field Name Description
0:28 DAB Double-word address to be compared.
29 BT Translation enabled.
30 DW Data store enabled.
31 DR Data read enabled.