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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umTOC.fm.(1.2)
March 27, 2006
Page 5 of 377
2.3.6.1 System Linkage Instructions—OEA ............................................................................. 118
2.3.6.2 Processor Control Instructions—OEA .......................................................................... 118
2.3.6.3 Memory Control Instructions—OEA ............................................................................. 119
2.3.7 Recommended Simplified Mnemonics ................................................................................ 120
3. Instruction-Cache and Data-Cache Operation .................................................... 121
3.1 Data-Cache Organization .............................................................................................................. 123
3.2 Instruction-Cache Organization ..................................................................................................... 124
3.3 Memory and Cache Coherency .................................................................................................... 125
3.3.1 Memory/Cache Access Attributes (WIMG Bits) ................................................................... 125
3.3.2 MEI Protocol ........................................................................................................................ 126
3.3.2.1 MEI Hardware Considerations ..................................................................................... 128
3.3.3 Coherency Precautions in Single-Processor Systems ........................................................ 129
3.3.4 Coherency Precautions in Multiprocessor Systems ............................................................ 129
3.3.5 PowerPC 750GX-Initiated Load/Store Operations .............................................................. 130
3.3.5.1 Performed Loads and Stores ....................................................................................... 130
3.3.5.2 Sequential Consistency of Memory Accesses ............................................................. 130
3.3.5.3 Atomic Memory References ......................................................................................... 130
3.4 Cache Control ............................................................................................................................... 131
3.4.1 Cache-Control Parameters in HID0 ..................................................................................... 131
3.4.1.1 Data-Cache Flash Invalidation ..................................................................................... 132
3.4.1.2 Enabling and Disabling the Data Cache ....................................................................... 132
3.4.1.3 Locking the Data Cache ............................................................................................... 132
3.4.1.4 Instruction-Cache Flash Invalidation ............................................................................ 133
3.4.1.5 Enabling and Disabling the Instruction Cache .............................................................. 133
3.4.1.6 Locking the Instruction Cache ...................................................................................... 133
3.4.2 Cache-Control Instructions .................................................................................................. 133
3.4.2.1 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) ...... 134
3.4.2.2 Data Cache Block Zero (dcbz) ..................................................................................... 134
3.4.2.3 Data Cache Block Store (dcbst) .................................................................................. 135
3.4.2.4 Data Cache Block Flush (dcbf) .................................................................................... 135
3.4.2.5 Data Cache Block Invalidate (dcbi) ............................................................................. 135
3.4.2.6 Instruction Cache Block Invalidate (icbi) ...................................................................... 136
3.5 Cache Operations ......................................................................................................................... 136
3.5.1 Cache-Block-Replacement/Castout Operations .................................................................. 136
3.5.2 Cache Flush Operations ...................................................................................................... 138
3.5.3 Data-Cache Block-Fill Operations ....................................................................................... 139
3.5.4 Instruction-Cache Block-Fill Operations .............................................................................. 139
3.5.5 Data-Cache Block-Push Operations .................................................................................... 139
3.6 L1 Caches and 60x Bus Transactions .......................................................................................... 139
3.6.1 Read Operations and the MEI Protocol ............................................................................... 140
3.6.2 Bus Operations Caused by Cache-Control Instructions ...................................................... 141
3.6.3 Snooping ............................................................................................................................. 142
3.6.4 Snoop Response to 60x Bus Transactions ......................................................................... 143
3.6.5 Transfer Attributes ............................................................................................................... 145
3.7 MEI State Transactions ................................................................................................................. 147
4. Exceptions ............................................................................................................... 151
4.1 PowerPC 750GX Microprocessor Exceptions ............................................................................... 152