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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
L2 Cache
Page 332 of 377
gx_09.fm.(1.2)
March 27, 2006
The dcbz instruction has no effect on the L2-cache state, whether the state is locked or not. The dcbi instruc-
tion causes invalidation of the block in the case of an L2 hit, for both normal and locked caches.
9.7 Data-Only and Instruction-Only Modes
The 750GX microprocessor supports a data-only mode of L2 operation that can be used for test (as
described in Section 9.8.2 on page 333) or for specific applications that might perform better when the L2 is
used to store only data. This mode is selected by setting the L2CR[DO] bit to 1. In L2 data-only mode, all
requests from the L1 instruction cache are treated as cache-inhibited, and so bypass the L2 and are
forwarded to the external bus. Once the L2CR[DO] bit is set, instructions currently in the L2 cache are not
accessible. Over time, cache lines containing instructions will be replaced with those containing data.
Similarly, the 750GX microprocessor supports an instruction-only mode of L2 operation, selected by setting
the L2CR[IO] bit to 1. In this mode, all requests from the L1 data cache are treated as cache inhibited by the
L2 cache. When L2CR[IO] is set, any L2-cache lines containing data will be replaced over time with those
containing instructions, until, in steady state, the L2 cache contains only instructions.
9.8 L2 Cache Test Features and Methods
In the course of system power-up, testing might be required to verify the proper operation of the L2 tag
memory, SRAM, and overall L2-cache system. The following sections describe the 750GX’s features and
methods for testing the L2 cache. The L2-cache address space should be marked as guarded (G = 1) so
spurious load operations are not forwarded to the 60x bus interface before branch resolution during L2-cache
testing.
9.8.1 L2CR Support for L2 Cache Testing
L2CR[DO] and L2CR[TS] support the testing of the L2 cache. L2CR[DO] prevents instructions from being
cached in the L2. This allows the L1 instruction cache to remain enabled during the testing process without
having L1 instruction misses affect the contents of the L2 cache. It also allows all L2-cache activity to be
controlled by program-specified load-and-store operations.
L2CR[TS] is used with the dcbf and dcbst instructions to push data into the L2 cache. When L2CR[TS] is
set, and the L1 data cache is enabled, an instruction loop containing a dcbf instruction can be used to store
any address or data pattern to the L2 cache. Additionally, 60x bus broadcasting is inhibited when a dcbz
instruction is executed. This allows the use of a dcbz instruction to clear an L1-cache block, followed by a
dcbf instruction to push the cache block into the L2 cache and invalidate the L1-cache block.
When the L2 cache is enabled, cacheable single-beat read operations are allowed to hit in the L2 cache, and
cacheable write operations are allowed to modify the contents of the L2 cache when a hit occurs. Cacheable
single-beat reads and writes occur when address translation is disabled, which invokes the use of the default
WIMG bits (0011). They also occur when address translation is enabled and accesses are marked as cache-
able through the page table entries or the Block Address Translation (BAT) Registers, and the L1 data cache
is disabled or locked. When the L2 cache has been initialized and the L1 cache has been disabled or locked,
load or store instructions then bypass the L1 cache and hit in the L2 cache directly. When L2CR[TS] is set,
cacheable single-beat writes are inhibited from accessing the 60x bus interface after an L2-cache miss.
During L2-cache testing, the performance monitor can be used to count L2-cache hits and misses, thereby
providing a numerical signature for test routines and a way to verify proper L2-cache operation.