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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_03.fm.(1.2)
March 27, 2006
Instruction-Cache and Data-Cache Operation
Page 131 of 377
atomic access to noncoherent memory. For detailed information on these instructions, see Chapter 2, Pro-
gramming Model, on page 57.
The lwarx instruction performs a load word from memory operation and creates a reservation for the 32-byte
section of memory that contains the accessed word. The reservation granularity is 32 bytes. The lwarx
instruction makes a nonspecific reservation with respect to the executing processor and a specific reservation
with respect to other masters. This means that any subsequent stwcx. executed by the same processor,
regardless of address, will cancel the reservation. Also, any bus write or invalidate operation from another
processor to an address that matches the reservation address will cancel the reservation.
The stwcx. instruction does not check the reservation for a matching address. The stwcx. instruction is only
required to determine whether a reservation exists. The stwcx. instruction performs a store word operation
only if the reservation exists. If the reservation has been cancelled for any reason, then the stwcx. instruction
fails and clears the CR0[EQ] bit in the Condition Register. The architectural intent is to follow the lwarx and
stwcx. instruction pair with a conditional branch, which checks to see whether the stwcx. instruction failed.
If the page table entry is marked caching-enabled (WIMG = x0xx), and an lwarx access misses in the cache,
then the 750GX performs a cache-block fill. If the page is marked caching-inhibited (WIMG = x1xx) or the
cache is locked, and the access misses, then the lwarx instruction appears on the bus as a single-beat load.
All bus operations that are a direct result of either an lwarx instruction or an stwcx. instruction are placed on
the bus with a special encoding. Note that this does not force all lwarx instructions to generate bus transac-
tions, but rather provides a means for identifying when an lwarx instruction does generate a bus transaction.
If an implementation requires that all lwarx instructions generate bus transactions, then the associated pages
should be marked as caching-inhibited.
The 750GX’s data cache treats all stwcx. operations as write-through independent of the WIMG settings.
However, if the stwcx. operation hits in the 750GX’s L2 cache, then the operation completes with the reser-
vation intact in the L2 cache. See Chapter 9, L2 Cache, on page 323 for more information. Otherwise, the
stwcx. operation continues to the bus interface unit for completion. When the write-through operation
completes successfully, either in the L2 cache or on the 60x bus, then the data-cache entry is updated
(assuming it hits), and CR0[EQ] is modified to reflect the success of the operation. If the reservation is not
intact, the stwcx. completes in the bus interface unit without performing a bus transaction, and without modi-
fying either of the caches.
3.4 Cache Control
The 750GX’s L1 caches are controlled by programming specific bits in the HID0 Special-Purpose Register
and by issuing dedicated cache-control instructions. Section 3.4.1 describes the HID0 cache-control bits, and
Section 3.4.2 on page 133 describes the cache-control instructions.
3.4.1 Cache-Control Parameters in HID0
The HID0 Special-Purpose Register contains several bits that invalidate, disable, and lock the instruction and
data caches. The following sections describe these facilities.