Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
PowerPC 750GX Overview
Page 26 of 377
gx_01.fm.(1.2)
March 27,2006
made available from the instruction cache. Typically, if a fetch access hits the BTIC, it provides
the first two instructions in the target stream effectively yielding a zero-cycle branch.
• 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—not-
taken, strongly not-taken, taken, strongly taken.
• Removal of Branch instructions that do not update the Count Register (CTR) or Link Register
(LR) from the instruction stream.
– Two integer units (IUs) that share 32 general purpose registers (GPRs) for integer operands.
• IU1 can execute any integer instruction.
• IU2 can execute all integer instructions except multiply and divide instructions (multiply, divide,
shift, rotate, arithmetic, and logical instructions). Most instructions that execute in the IU2 take
one cycle to execute. The IU2 has a single-entry reservation station.
– 3-stage floating-point unit (FPU).
• FPU fully compliant with IEEE
®
754-1985 for both single-precision and double-precision opera-
tions.
• Support for non-IEEE mode for time-critical operations.
• Hardware support for denormalized numbers.
• Hardware support for divide.
• 2-entry reservation station.
• Thirty-two 64-bit Floating Point Registers (FPRs) for single and double-precision operations.
– 2-stage load/store unit (LSU).
• 2-entry reservation station.
• 4-entry load queue.
• Single-cycle, pipelined cache access.
• Dedicated adder performs effective address (EA) calculations.
• Performs alignment and precision conversion for floating-point data.
• Performs alignment and sign extension for integer data.
• 3-entry store queue.
• Supports both big-endian and little-endian modes.
– System register unit (SRU) handles miscellaneous instructions.
• Executes Condition Register (CR) logical and Move-to/Move-from SPR instructions (mtspr and
mfspr).
• Single-entry reservation station.
• Rename buffers.
– Six GPR rename buffers.
– Six FPR rename buffers.
– Condition Register buffering supports two CR writes per clock.
• Completion unit.
– The completion unit retires an instruction from the 6-entry reorder buffer (completion queue) when all
instructions ahead of it have been completed, the instruction has finished execution, and no excep-
tions are pending.
– Guarantees a sequential programming model and a precise-exception model.
– Monitors all dispatched instructions and retires them in order.
– Tracks unresolved branches and flushes instructions from the mispredicted branch path.