Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_10.fm.(1.2)
March 27, 2006
Power and Thermal Management
Page 345 of 377
10.4.2.1 TAU Single-Threshold Mode
When the TAU is configured for single-threshold mode, either THRM1 or THRM2 can be used to contain the
threshold value, and a thermal-management interrupt is generated when the threshold value is crossed. To
configure the TAU for single-threshold operation, set the desired temperature threshold, the thermal-manage-
ment interrupt direction (TID), thermal-management interrupt enable (TIE), and SPR valid (V) bits for either
THRM1 or THRM2. The unused THRMn threshold SPR should be disabled by clearing the V bit to 0. In this
discussion, THRMn refers to the THRM threshold SPR (THRM1 or THRM2) selected to contain the active
threshold value.
After setting the desired operational parameters, the TAU is enabled by setting the THRM3[E] bit to 1, and
placing a value that allows a sample interval of 20 microseconds or greater in the THRM3[SITV] field. The
THRM3[SITV] setting determines the number of processor clock cycles between input to the DAC and
sampling of the comparator output. Accordingly, the use of a value smaller than recommended in the
THRM3[SITV] field can cause inaccuracies in the sensed temperature.
If the junction temperature does not cross the programmed threshold, the thermal-management interrupt bit
(THRMn[TIN]) is cleared to 0 to indicate that no interrupt is required, and the thermal-management interrupt
valid bit (THRMn[TIV]) is set to 1 to indicate that the TIN bit state is valid. If the threshold value has been
crossed, the THRMn[TIN] and THRMn[TIV] bits are set to 1, and a thermal-management interrupt is gener-
ated if both the THRMn[TIE] and MSR[EE] bits are set to 1.
A thermal-management interrupt is held asserted internally until recognized by the 750GX’s interrupt unit.
Once a thermal-management interrupt is recognized, further temperature sampling is suspended, and the
THRMn[TIN] and THRMn[TIV] values are held until an mtspr instruction is executed to THRMn.
The execution of an mtspr instruction to THRMn anytime during TAU operation will clear the THRMn[TIV] bit
to 0 and restart the temperature comparison. Executing an mtspr instruction to THRM3 will clear both
THRM1[TIV] and THRM2[TIV] bits to 0, and restart temperature comparison in THRMn if the THRM3[E] bit is
set to 1.
Examples of valid THRM1 and THRM2 bit settings are shown in Table 10-3.
Table 10-3. Valid THRM1 and THRM2 Bit Settings
(Page 1 of 2)
TIN
1
TIV
1
TID TIE V Description
xxxx0The threshold in the SPR will not be used for comparison.
xxx01
Threshold is used for comparison; thermal-management interrupt assertion is dis-
abled.
xx001
Set TIN, and do not assert thermal-management interrupt if the junction temperature
exceeds the threshold.
xx011
Set TIN, and assert thermal-management interrupt if the junction temperature
exceeds the threshold.
xx101
Set TIN, and do not assert thermal-management interrupt if the junction temperature
is less than the threshold.
xx111
Set TIN, and assert thermal-management interrupt if the junction temperature is less
than the threshold.
x 0 x x 1 The state of the TIN bit is not valid.
Note:
1. The TIN and TIV bits are read-only status bits.