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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
L2 Cache
Page 330 of 377
gx_09.fm.(1.2)
March 27, 2006
9.6 L2 Cache Used as On-Chip Memory
The L2 cache can be configured to be unlocked, partially locked, or completely locked. When configured to
be unlocked, the L2 cache is 4-way set-associative, with 32 bytes per sector, two sectors per block. When
configured to be completely locked, the L2 cache is a 1-MB on-chip memory (OCM) that is explicitly managed
by software. With one, two, or three ways locked, the locked partition is a software managed OCM, while the
unlocked partition is a 3-, 2-, or 1-way (direct mapped) cache that is managed by hardware. The locked cache
is considered to be local memory, and so is not kept coherent with main memory.
9.6.1 Locking the L2 Cache
Locking of the L2 cache is controlled by the L2CR[LOCK] bits (bits 24:27) as follows:
• 0000 No cache locking
• 1xxx Lock way 0
• x1xx Lock way 1
• xx1x Lock way 2
• xxx1 Lock way 3
Note: L2CR[LOCKLO] and L2CR[LOCKHI] can also be used to lock ways 0 and 1, and ways 2 and 3, respec-
tively. These bits are defined in this way to provide a form of backward compatibility with the 750FX design.
However, new software should use the L2CR[LOCK] bits to control L2-cache locking.
Any cache line in a locked part of the L2-cache array can be read or written by the processor, but cannot be
deallocated for line replacement. The locked L2 cache is intended to be a local memory for the processor,
and so should not contain addresses that are accessed outside the processor. However, the L2 controller
does snoop the locked ways, and a snoop hit can cause a deallocation. In addition, for the specific case of an
stwcx. marked write through that hits in a locked line, the line will be invalidated in the L2 cache. In this case,
the store will be forwarded to the bus, as is the case for the unlocked L2. Finally, invalid lines in the locked
part cannot be allocated by any mechanism.
To lock instructions or data in way 0 of the L2 cache requires the following sequence:
1. Execute a sync instruction to allow all load/store activity to complete.
2. Set the data-only bit (L2CR[DO] = 1) to prevent the current instruction stream from being cached in
the L2.
3. Flush the L2 to save any modified data.
4. Disable the L2 as usual for invalidation.
5. Invalidate the L2 to prevent collisions with lines to be locked.
6. Lock ways 1 through 3 (L2CR[LOCK] = 0111) so all allocations are in way 0.
7. Enable the L2.
8. Load the contents to be locked (see Section 9.6.1.1).
9. Execute a sync instruction
10. Lock way 0 and unlock ways 1 through 3 (L2CR[LOCK] = 1000).
11. Reset the data-only bit (L2CR[DO] = 0).
At this point, all data and instructions to be locked are in way 0 of the L2 cache. To lock multiple ways, first
unlock the ways that are to be locked, and lock all others as described in step 6. Then, lock the selected ways
and unlock all others as described in step 10.