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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 306 of 377
gx_08.fm.(1.2)
March 27, 2006
For read bursts, DRTRY can be asserted one bus clock cycle after TA is asserted to signal that the data
presented with TA
is invalid and that the processor must wait for the negation of DRTRY before forwarding
data to the processor (see Figure 8-14). Thus, a data beat can be terminated by a predicted branch with TA
,
and then one bus clock cycle later confirmed with the negation of DRTRY
. The DRTRY signal is valid only for
read transactions. TA
must be asserted on the bus clock cycle before the first bus clock cycle of the assertion
of DRTRY
; otherwise, the results are undefined.
The DRTRY
signal extends data-bus mastership such that other processors cannot use the data bus until
DRTRY
is negated. Therefore, in the example in Figure 8-14, data-bus tenure for the next transaction cannot
begin until bus clock cycle 6. This is true for both read and write operations even though DRTRY
does not
extend bus mastership for write operations.
Figure 8-14. Termination with DRTRY
12 345
TS
qual DBG
DBB
data
ta
drtry