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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_10.fm.(1.2)
March 27, 2006
Power and Thermal Management
Page 339 of 377
10.2.1.4 Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units are disabled. To
conserve the maximum amount of power, the PLL can be disabled by placing the PLL_CFG signals in the
PLL bypass mode, and disabling SYSCLK.
Note: Forcing the SYSCLK signal into a static state does not disable the 750GX’s PLL, which will continue to
operate internally at an undefined frequency unless placed in PLL bypass mode.
Due to the fully static design of the 750GX, internal processor state is preserved when no internal clock is
present. Because the time base and decrementer are disabled while the 750GX is in sleep mode, the
750GX’s time-base contents will have to be updated from an external time base after exiting sleep mode if
maintaining an accurate time-of-day is required. Before entering the sleep mode, the 750GX asserts the
QREQ
signal to indicate that it is ready to disable bus snooping.
When the system has ensured that snooping is no longer necessary, it asserts QACK
and the 750GX will
enter sleep mode. Sleep mode can be summarized as follows:
• All functional units disabled (including bus snooping and time base/decrementer).
• All nonessential input receivers disabled.
– Internal clock regenerators disabled.
– PLL still running (see below).
• Sleep mode is enabled with the following sequence:
1. Set sleep bit (HID0[10] = 1); clear doze and nap bits (HID0[8] and HID0[9]).
2. 750GX asserts quiesce request (QREQ
).
3. System asserts quiesce acknowledge (QACK
).
4. 750GX enters sleep mode after several processor clocks.
• Several methods of returning to full-on mode:
– Assert INT
, SMI, or MCP interrupts.
– Assert hard reset or soft reset.
• PLL can be disabled and SYSCLK can be removed while in sleep mode.
• Return to full-on mode after PLL and SYSCLK are disabled in sleep mode:
– Enable SYSCLK.
– Reconfigure PLL into desired processor clock mode.
– System logic waits for PLL start-up and relock time (100 µs).
– System logic asserts one of the sleep recovery signals (for example, INT
).
10.2.1.5 Dynamic Power Reduction
The 750GX functional units will go into a low power mode automatically if the unit is idle. This mode will not
affect operational performance and is entered when the DPM bit is enabled in HID0 (HID0 bit 11). This oper-
ation is transparent to software or any external hardware.