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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 314 of 377
gx_08.fm.(1.2)
March 27, 2006
Figure 8-21 shows the use of data-delay controls with burst transfers. Note that all bidirectional signals are
tristated between bus tenures. Also note:
• The first data beat of burst read data (clock 0) is the critical quadword.
• The write burst shows the use of TA
signal negation to delay the third data beat.
• The final read burst shows the use of DRTRY
on the third data beat.
• The address for the third transfer is delayed until the first transfer completes.
Figure 8-21. Burst Transfers with Data-Delay Controls
BR
BG
ABB
TS
A[0–31]
TT[0–4]
TBST
GBL
AACK
ARTRY
DBG
DBB
D[0–63]
TA
DRTRY
TEA
CPU A
In 0
1234567891011121314151617181920
1234567891011121314151617181920
CPU A CPU A
Read Write Read
In 1 In 2 In 3 Out 0 Out 1 Out 2
Out 3
In 0 In 1 In 2 In 3In 2