Filter
Top Products
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_03.fm.(1.2)
March 27, 2006
Instruction-Cache and Data-Cache Operation
Page 145 of 377
3.6.5 Transfer Attributes
In addition to the address and transfer type signals, the 750GX supports the transfer attribute signals: TBST
,
TSIZ[0–2], WT
, CI, and GBL. The TBST and TSIZ[0–2] signals indicate the data-transfer size for the bus
transaction.
The WT
signal reflects the write-through status (the complement of the W bit) for the transaction as deter-
mined by the MMU address translation during write operations. WT
is asserted for burst writes due to dcbf
(flush) and dcbst (clean) instructions, and for snoop pushes; WT
is negated for External Control Out Word
Indexed (ecowx) transactions. Since the write-through status is not meaningful for reads, the 750GX uses
the WT
signal during read transactions to indicate that the transaction is an instruction fetch (WT negated), or
not an instruction fetch (WT
asserted).
The CI
signal reflects the caching-inhibited/enabled status (the complement of the I bit) of the transaction as
determined by the MMU address translation even if the L1 caches are disabled or locked. CI
is always
asserted for External Control In Word Indexed (eciwx) and ecowx bus transactions independent of the
address translation.
The GBL
signal reflects the memory coherency requirements (the complement of the M bit) of the transaction
as determined by the MMU address translation. Castout and snoop copy-back operations (TT[0–4] = 00110)
are generally marked as nonglobal (GBL
negated) and are not snooped (except for reservation monitoring).
Other masters, however, might perform direct memory access (DMA) write operations with this encoding but
marked global (GBL
asserted); thus, the operation must be snooped.
Table 3-6 summarizes the address and transfer attribute information presented on the bus by the 750GX for
various master or snoop-related transactions.
Read-with-no-intent-to-cache
(RWNITC)
01011
A RWNITC operation is issued to acquire exclusive use of a memory location with
no intention of modifying the location.
• If the addressed cache block is in the exclusive (E) state, the cache block
remains in the exclusive (E) state.
• If the addressed cache block is in the modified (M) state, the 750GX asserts
ARTRY
and initiates a push of the modified block out of the cache, and the
cache block is placed in the exclusive (E) state.
• If the address misses in the cache, no action is taken.
Reserved 01111 —
Reserved 1XX11 —
Table 3-5. Response to Snooped Bus Transactions (Page 3 of 3)
Snooped Transaction TT[0–4] 750GX Response