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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
PowerPC 750GX Overview
Page 52 of 377
gx_01.fm.(1.2)
March 27,2006
1.8.2 750GX Microprocessor Memory-Management Implementation
The 750GX implements separate MMUs for instructions and data. It implements a copy of the Segment
Registers in the instruction MMU. However, read and write accesses (Move-from Segment Register [mfsr]
and Move-to Segment Register [mtsr]) are handled through the Segment Registers implemented as part of
the data MMU. The 750GX MMU is described in Section 1.2.3, Memory Management Units (MMUs), on
page 32.
The R (referenced) bit is set in the PTE in memory during a page table search due to a TLB miss. Updates to
the changed (C) bit are treated like TLB misses. The page table is searched again to find the correct PTE to
update when the C bit changes from 0 to 1.
1.9 Instruction Timing
The 750GX is a pipelined, superscalar processor. A pipelined processor is one in which instruction
processing is divided into discrete stages, allowing work to be done on multiple instructions in each stage. For
example, after an instruction completes one stage, it can pass on to the next stage leaving the previous stage
available to a subsequent instruction. This improves overall instruction throughput.
A superscalar processor is one that issues multiple independent instructions to separate execution units in a
single cycle, allowing multiple instructions to execute in parallel. The 750GX has six independent execution
units, two for integer instructions, and one each for floating-point instructions, branch instructions, load-and-
store instructions, and system-register instructions. Having separate GPRs and FPRs allows integer, floating-
point calculations, and load-and-store operations to occur simultaneously without interference. Additionally,
rename buffers are provided to allow operations to post completed results for use by subsequent instructions
without committing them to the architected FPR and GPR register files.
As shown in Figure 1-5 on page 53, the common pipeline of the 750GX has four stages through which all
instructions must pass—fetch, decode/dispatch, execute, and complete/write back. Instructions flow sequen-
tially through each stage. However, at dispatch, a position is made available in the completion queue at the
same time it enters the execution stage. This simplifies the completion operation when instructions are retired
in program order. Both the load/store and floating-point units have multiple stages to execute their instruc-
tions. An instruction occupies only one stage at a time in all execution units. At each stage, an instruction
might proceed without delay or might stall. Stalls are caused by the requirement for additional processing or
other events. For example, divide instructions require multiple cycles to complete the operation; load-and-
store instructions might stall waiting for address translation (during TLB reload or page fault, for example).